ENGINEERING TRAINING COURSE
Wafer Failure Analysis
for Yield Enhancement
Semiconductor failure analysis has changed dramatically in the last five years. New technology and higher complexity have challenged traditional methods beyond their limits. However, new diagnostic tools are expensive and cannot do the job alone.
Failure analysis steps beyond the results of statistical tools and parametric testing and is still the most economical way to understand yield and reliability problems and to identify their causes.
This seminar addresses failure analysis as it is today. All failure sources from design to field application are addressed. Powerful fault location tools are introduced to provide the understanding required for their effective application. Traditional failure analysis techniques, still essential to proceed from symptom diagnosis to conclusion and corrective action, are explained in detail.
This 4 day course is designed to give engineers and technicians a comprehensive overview of manufacturing defects and failure mechanisms. Characteristics of failure mechanisms are well explained in the updated course text, Wafer Failure Analysis for Yield Enhancement.
We give the background needed to effectively monitor and support outside services or to perform the analysis “hands on.” Case studies illustrate practical techniques for solving real problems. Participants are encouraged to present real problems for discussion.
Who Should Attend
Anyone working to solve reliability or yield problems in semiconductor products will find this course valuable.
Failure analysts will gain perspective as well as an understanding of specific powerful techniques. Foundry users, designers, and assembly personnel will benefit from understanding failure mechanisms and the failure analysis process.
This course will benefit companies and people having a role in the problem solving process.
Glasgow, Scotland is easily reached from many European and USA cities direct by air. The city centre is served by two main railway stations; Queen Street and Central.
Glasgow is one of the liveliest and most cosmopolitan destinations in Europe. The city has been reborn as a centre of style and vitality set against a backdrop of outstanding Victorian architecture. Glasgow boasts world famous art collections, the best shopping in the United Kingdom outside London, and the most vibrant nightlife in Scotland.
Art and culture are important in Glasgow life with more than 20 galleries and museums, including the world famous Burell Collection and the newly refurbished Kelvingrove Art Gallery & Museum. No visit would be complete without experiencing the city's shopping with high street stores, designer labels, and speciality outlets to explore, with welcome pit-stops in the first class café culture around the Italian Centre, Merchant Square and Gallery of Modern Art
Attendee Cost $1800.00
CALL SGT on 0141 550 2378
or firstname.lastname@example.org for more information, registration details etc
September 14-17, 2009
Basic Reliability Concepts
Early, Intrinsic, Wearout Failure
Stress and Acceleration Factors
Failure Analysis Procedures
Introduction: Terms and Concepts
Yield and Defect Mechanisms
Latchup, EOS, ESD
Process Induced Charges
Masking and Etch Issues
Electrical Fault Isolation
Semiconductor Parametrics (Test Structures)
Test Binning, Loop on Problem Vectors
IDD / IDDQ
Curve Tracer Testing
Physical Fault Localization
Liquid Crystal Hot Spot Detection
Fluorescent Microthermal Imaging
SEM: Basic, Voltage Contrast, EBIC, RBI,
Emission Microscopy, IR Thermography
Laser Stimulation Techniques
Sample Preparation Techniques
Cross Section / Parallel Polish
Selected Area Polishing
Backside Polish (for emission, etc.)
Chemical Etching / Deprocessing
Focused Ion Beam (FIB)
Plasma Etch / RIE
EDS, Auger, SIMS, XPS
In-house / Off-site
User / Foundry
Course Instructor / Author
DAVID BURGESS, owner, Accelerated Analysis.
Dave Burgess has worked in failure analysis since earning BEE and MSEE degrees from Rensselaer Polytechnic Institute and San Jose State College respectively. As the Hewlett-Packard corporate reliability physicist for nearly 15 years, he was responsible for training and development of failure analysis capability company wide.
He is co-author of Wafer Failure Analysis for Yield Enhancement. His analysis tools are in worldwide use. He has authored papers and served active roles at both ISTFA (International Symposium for Testing and Failure Analysis) and at IRPS (International Reliability Physics Symposium). He is a Senior Member of IEEE, past general chairman of IRPS and a charter member of EDFAS, the Electronic Device Failure Analysis Society.